1. Technical Field
The present invention relates to voltage level switching and, more particularly to a voltage level shifter circuit and a method for the operation of the voltage level shifter circuit.
2. Description of Related Art
Reference is now made to FIG. 1 which shows a current mirror circuit 10 according to conventional art. The base of a transistor Q1 is connected to the base of a transistor Q2, along with both of the emitters of Q1 and Q2 typically connected to ground or another common voltage point. A link connects the collector of Q1 to the bases of Q1 and Q2. The collector of Q1 also connects to voltage supply (Vcc) via a resistor R. The voltage output (Vout) of current mirror circuit 10 is between the collector of Q2 and ground or between the collector of Q2 and another voltage point.
Bipolar transistors such as Q1 or Q2 have a current gain (β) which is the ratio of the collector current to the base current. The relationship between IREF and IOUT is given by equation Eq. 1 below:
                              I          OUT                =                              (                          β                              β                +                2                                      )                    ⁢                      I            REF                                              Eq        .                                  ⁢        1            
Where the current gain (β) is high IREF equals IOUT and IREF is said to ‘mirror’ IOUT. The current being ‘mirrored’ can be, and sometimes is, a varying signal current. The current mirror is typically used to provide bias currents and active loads to circuits. Current mirrors may typically be constructed using various types of semiconductor switches such as a metal oxide semiconductor field effect transistor (MOSFET), field effect transistor (FET), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT) or Schottky transistor.
Reference is now made to FIG. 2 which shows a level shifter circuit 20 according to conventional art. Level shifter circuit 20 includes inverting amplifier A, resistors R1 and R2 (or equivalent loads), switches TCM1, TCM2, T1 and T2 which are preferably insulated gate field effect transistors (IGFETs). A current mirror circuit in level shifter circuit 20 is shown with the gate of IGFET TCM1 is connected to the gate (G) of a IGFET TCM2, along with both of the sources (S) of TCM1 and TCM2 typically connected to ground. A link connects the drain (D) of TCM1 to the gates (G) of TCM1 and TCM2. The drain (D) of TCM1 also connects to voltage supply (Vcc) via a resistor (not shown) to form current source I.
The drain of TCM2 connect to the sources (S) of IGFETS T1 and T2. The drain (D) of T1 connects to voltage supply (Vcc) through resistor R1. The drain (D) of T2 connects to voltage supply (Vcc) through resistor R2. The floating output voltage (Vf) of circuit 20 may be between voltage supply (Vcc) and node X or may be between voltage supply (Vcc) and node Y. Voltage input terminal (Control) is connected to the gate (C) of IGFET T2 and an inverse of voltage input terminal (Control) is connected to the gate (G) of IGFET T1 via inverting amplifier A.
In operation, shifter circuit 20 current I flows through resistors R1 or R2 which are referenced to floating output voltage (Vf) by virtue of current I flowing through resistors R1 or R2. The switching time for IGFETs T1 and T2 is typically a function of the miller drain capacitors of T1 and T2 plus all parasitic capacitances of T1 and T2 that are charged by the current I to a voltage swing value of the voltage input terminal (Control). IGFET T1 and resistor R1 are connected in circuit 20 as a common source (S) amplifier with output on node X common to the input from voltage input terminal Control. Similarly, IGFET T2 and resistor R2 are connected in circuit 20 as a common source (S) amplifier with output on node Y common to the inverse of input voltage input terminal Control. The bandwidth of the common-source amplifier typically tends to be low, due to high capacitance resulting from the Miller effect. The Miller effect accounts for the increase in the equivalent input capacitance of a common source (S) amplifier due to amplification of the capacitance between the input and output terminals. The additional input charge (QCM) due to the Miller effect for both IGFETs T1 or T2 is given by equation Eq. 2 below:
                              Q          CM                =                                            ⅆ              V                                      ⅆ              t                                ⁢                      (                                          C                GD                            +                              C                DS                            +                              C                P                                      )                                              Eq        .                                  ⁢        2            CP=Parasitic capacitance of the drain (D) of T1 or T2CGD=The capacitance between gate (C) and drain (D) of T1 or T2CDS=The capacitance between drain (D) and source (S) of T1 or T2V=Voltage at node X for T1 or voltage at node Y for T2
Where even a small parasitic capacitance CGD between gate (G) and drain (D) may become a large influence in the frequency response and hence bandwidth of the common source amplifier. A low bandwidth due to the effect of Miller capacitance typically reduces switching speed of the common source amplifier. Additionally, with a level shifter like shifter circuit 20, the switching times of IGFETs T1 and T2 are typically proportional to current consumption in resistors R1 and R2 because current in resistors R1 and R2 charges the Miller capacitance (CM=CP+CGD+CDS).
The terms “field-effect transistor (FET) switch” is used herein interchangeably and equivalently with the term “bipolar junction transistor (BJT) switch”. Whereby the gate of the FET switch is equivalent to the base of the BJT switch, the drain of the FET switch is equivalent to the collector of the BJT switch and the source of the FET switch is equivalent to the emitter of the BJT switch.
The term “leg of a switch” as used herein, refers to the actuation of a gate (of an FET) by application of a voltage to the gate for example, which causes a reduction in impedance between a drain and a source (of the FET). The reduction in impedance between the drain and the source (of the FET) is considered equivalent to the connection together of two contacts of a mechanical switch (e.g. single pole double throw switch (SPDT)).
The terms “charging” and “discharging” in the context of the present invention in reference to charging and discharging a capacitor, are used herein interchangeably except that current flow while charging and discharging is usually in the opposite direction.
The term “switch” as used herein refers to any of: silicon controlled rectifier (SCR), insulated gate bipolar junction transistor (IGBT), insulated gate field effect transistor (IGFET), bipolar junction transistor (BJT), field effect transistor (FET), junction field effect transistor (JFET), switching diode, mechanically operated single pole double pole switch (SPDT), SPDT electrical relay, SPDT reed relay, SPDT solid state relay, insulated gate field effect transistor (IGFET), diode for alternating current (DIAC), and triode for alternating current (TRIAC).
An ideal switch takes no time to go from off to on or from on to off. The switching time of the ideal switch is therefore zero. The term “switching time” as used herein refers to a finite period of time it takes for a switch to go from being in an “off” state to an “on” state or from the “on” state to the “off” state.
The terms “on” and “off” as used herein, when applied to a switch, refer to an increased current value flowing through the switch when the switch is “on” compared to the relative decreased current value flowing through the switch when the switch is “off”.
The term “minimal current” as used herein refers to the relative decreased current value flowing through a switch when the switch is off when compared to an increased current value flowing through the switch when the switch is on.